DM74LSAN Synchronous 4-Bit Binary Counter With Asynchronous Clear. These synchronous, presettable counters feature an internal carry look-ahead for . DM74LSAN datasheet, DM74LSAN circuit, DM74LSAN data sheet: NSC – Synchronous 4-Bit Binary Counters,alldatasheet, datasheet, Datasheet. DM74LSAN datasheet, DM74LSAN circuit, DM74LSAN data sheet: FAIRCHILD – Synchronous 4-Bit Binary Counters,alldatasheet, datasheet.
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The “Recommended Operating Conditions” table will define the conditions for actual device operation. Typical propagation ddm74ls161an, clock to Q output 14 ns. The input pulses are supplied by generators having the following characteristics: Carry output for n-bit cascading.
Index of /datasheet
Specify by appending the suffix letter “X” to the ordering code. Changes made to control inputs enable P or T or load that will modify the operating mode have no effect until clocking occurs. The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Search field Part name Part description. A buffered clock input triggers the four flip-flops on the rising positive-going edge of the clock input waveform.
The gate dm74s161an is connected to the clear input to synchronously clear the counter to all low outputs. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters. Clear Release Time Note 2. Free Air Operating Temperature.
The function of the counter whether enabled, dis- abled, loading, or counting will be dictated solely by the conditions meeting the stable set-up and hold times.
These counters are fully programmable; that is, the outputs may be preset to either level. Operating Free Air Temperature Range. Typical clock frequency 32 MHz.
The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Clear Release Time Note 3. These synchronous, presettable counters feature an inter- nal carry look-ahead for application in high-speed counting designs.
As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input. The clear function for the DM74LSA is synchronous; and a low level at the clear inputs sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of the enable inputs. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.
This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. Typical power dissipation 93 mW.
DM74LSAN Datasheet(PDF) – National Semiconductor (TI)
Enable P and enable T setup times are measured at t. The ripple carry output thus enabled will produce a high- level output pulse with a duration approximately equal to the high-level portion of the Q. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without addi- tional gating. Clock Frequency Note 3. The clear function datashet the DM74LSA is asynchro- nous; and a low level at the clear input sets all four of the flip-flop outputs LOW, regardless of the levels of clock, load, or enable inputs.
The device should not be operated at these datasheeet. Internal look-ahead dm74ls1161an fast counting. These counters feature a fully independent clock circuit. Synchronous operation is pro- vided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating.
Clock Frequency Note 2.
Devices also available in Tape and Reel. Vary PRR to measure f.